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? semiconductor components industries, llc, 2006 december, 2006 ? rev. 3 1 publication order number: ncp1027/d ncp1027 high?voltage switcher for medium power offline smps featuring low standby power the ncp1027 offers a new solution targeting output power levels from a few watts up to 15 w in a universal mains flyback application. our proprietary high?voltage technology lets us include a power mosfet together with a startup current source, all directly connected to the bulk capacitor. to prevent lethal runaway in low input voltage conditions, an adjust able brown?out circuitry blocks the activity until sufficient input level is reached. current?mode operation together with an adjustable ramp compensation offers superior performance in universal mains applications. furthermore, an over power protection pin brings the ability to precisely compensate all internal delays in high input voltage conditions and optimize the maximum output current capability. protection wise, a timer detects an overload or a short?circuit and stops all operations, ensuring a safe auto?recovery, low duty cycle burst operation. an integrated, auto?recovery, overvoltage protection permanently monitors the v cc level and temporarily shuts down the driving pulses in case of an unexpected feedback loop runaway. finally, a great r ds(on) figure makes the circuit an excellent choice for standby/auxiliary offline power supplies or appli cations requiring higher output power levels. features ? built?in 700 v mosfet with typical r ds(on) of 5.8 , t j = 25 c ? current?mode fixed frequency operation: 65 khz and 100 khz ? fixed peak current of 800 ma ? skip?cycle operation at low peak currents ? internal current source for clean and lossless startup sequence ? auto?recovery output short circuit protection with timer?based detection ? auto?recovery overvoltage protection with auxiliary winding operation ? programmable brown?out input for low input voltage detection ? programmable over power protection ? input to permanently latchoff the part ? internal frequency jittering for improved emi signature ? extended duty cycle operation to 80% typical ? no?load input standby power of 85 mw @ 265 vac ? 500 mw loaded, input power of 715 mw @ 230 vac ? these are pb?free devices typical applications ? medium power ac?dc adapters for chargers ? auxiliary/standby power supplies for atx and tvs power supplies reference 230 vac 90?265 vac ncp1027 ? 5.8 25 w* 15 w* *typical values, open?frame, 65 khz version, r ja < 75 c/w, t a = 50 c. 8?lead pdip p suffix case 626a pin connections device package shipping * ordering information ncp1027p065g pdip?8 (pb?free) 50 units / rail http://onsemi.com marking diagram xxx = 65 or 100 a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package (top view) ramp comp. v cc brown?out fb drain p1027pxxx awl yywwg gnd opp *for additional information on our pb?free strateg y and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. NCP1027P100G pdip?8 (pb?free) 50 units / rail
ncp1027 http://onsemi.com 2 85?265 vac + bo + ovp + 1 2 3 4 5 7 8 ncp1027 opp* + v ou t gn d figure 1. typical application ramp comp.* *optional component pin function description pin no. symbol function description 1 v cc powers the internal circuitry this pin is connected to an external capacitor of typically 22 f. the v cc includes an active shunt which serves as an auto?recovery overvoltage protection. 2 ramp comp. ramp compensation in ccm to extend the duty cycle operation in continuous conduction mode (ccm), pin 3 offers the ability to inject ramp compensation in the controller. if unused, short this pin to v cc . 3 brown?out brown?out and latchoff input by monitoring the bulk level via a resistive network, the circuit protects itself from low mains conditions. if an external event brings this pin above 4.0 v, the part fully latches off. 4 fb feedback signal input by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 5 drain drain connection the internal drain power switch circuit connection. ? ? ? this unconnected pin ensures adequate creepage distance. 7 opp over power protection driving this pin reduces the power supply capability in high line conditions. if no over power protection is needed, short this pin to ground. 8 gnd the ic ground ?
ncp1027 http://onsemi.com 3 v cc vclamp auto?recovery ovp + ? + ? + v cc mngt fault uvlos 4 v rst v dd ic1 gnd 20 s rc s q q r leb timer ip flag + ? v cc < 4 v reset ibo + vbo 65 khz or 100 khz clock s q q r jittering v dd bo ramp comp. + 25% of lp + ? v dd rfb fb skip + ? soft?start ip flag + ? opp v cc drain uvlo figure 2. internal block diagram + vlatch icomp max ip selection over power protection input ramp compensation 50 s rc
ncp1027 http://onsemi.com 4 maximum ratings rating symbol value unit power supply voltage on all pins, except pin 5 (drain) v cc ?0.3 to 10 v drain v oltage bvdss ?0.3 to 700 v maximum current into pin 1 when activating the 8.7 v active clamp i_v cc 15 ma thermal resistance, junction?to?air ? pdip7 r ja 100 c/w thermal resistance, junction?to?air ? pdip7 with 1.0 cm of 35 copper area r ja 75 c/w maximum junction t emperature tj max 150 c storage temperature range ? ?60 to +150 c esd capability, human body model (hbm) (all pins except hv) ? 2.0 kv esd capability, machine model (mm) ? 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil?std?883, method 3015. machine model method 200 v. 2. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78. electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 8.0 v, unless otherwise noted.) characteristic pin symbol min typ max unit supply section and v cc management v cc increasing level at which the switcher starts to operate 1 vcc on 7.9 8.5 8.9 v v cc decreasing level at which the switcher stops operation 1 vcc (min) 6.7 7.2 7.9 v hysteresis between vcc on and vcc (min) ? vcc hyste ? 1.2 ? v offset voltage above vcc on at which the internal clamp activates 1 vcc clamp 140 200 300 mv v cc voltage at which the internal latch is reset 1 vcc reset ? 4.0 ? v internal ic consumption, mosfet switching at 65 khz or 100 khz 1 icc1 ? 1.4 1.9 ma power switch circuit power switch circuit on?state resistance ncp1027 (id = 100 ma) t j = 25 c t j = 125 c 5 r ds(on) ? ? 5.8 9.8 7.0 11 power switch circuit and startup breakdown voltage (id (off) = 120 a, t j = 25 c) 5 bvdss 700 ? ? v power switch and startup breakdown voltage of f?state leakage current t j = 25 c (vds = 700 v) t j = 125 c (vds = 700 v) 5 5 idss(off) ? ? 50 30 ? ? a switching characteristics (rl = 50 , vds set for idrain = 0.7 x ilim) turn?on time (90%?10%) turn?off t ime (10%?90%) 5 5 t on t off ? ? 35 35 ? ? ns ns internal startup current source high?v oltage current source, v cc = vcc on ? 200 mv 1 ic1 3.5 6.0 8.0 ma high?v oltage current source, v cc = 0 1 ic2 350 650 900 a v cc transition level for ic1 to ic2 toggling point 1 v ccth ? 1.3 ? v
ncp1027 http://onsemi.com 5 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 8.0 v, unless otherwise noted.) characteristic pin symbol min typ max unit current comparator maximum internal current setpoint, pin 4 open, t j = 25 c, f sw = 65 khz (note 3) ? ipeak_27_cs_ 65 k 720 800 880 ma final switch current with a primary slope of 200 ma/ s, f sw = 65 khz (note 4) ? ipeak_27_sw_ 65 k ? 820 ? ma maximum internal current setpoint, pin 4 open, t j = 25 c, f sw = 100 khz (note 3) ? ipeak_27_cs_ 100 k 720 800 880 ma final switch current with a primary slope of 200 ma/ s, f sw = 100 khz (note 4) ? ipeak_27_sw_ 100 k ? 820 ? ma setpoint decrease for a pin 7 injected current of 40 a, t j = 25 c 7 iopp ? 23 ? % voltage level in pin 7 at which opp starts to operate 7 iopptripv ? 1.5 ? v soft?start duration ? t ss ? 1.0 ? ms propagation delay from current detection to drain off state ? t prop ? 100 ? ns leading edge blanking duration ? t leb ? 200 ? ns internal oscillator oscillation frequency (note 5) 65 khz version, t j = 25 c ? f osc 58.5 65 71.5 khz oscillation frequency (note 5) 100 khz version, t j = 25 c ? f osc 90 100 110 khz frequency jittering in percentage of f osc ? f jitter ? 6.0 ? % jittering swing frequency ? fswing ? 300 ? hz maximum duty cycle ? dmax 74 80 87 % feedback section internal pullup resistor 4 rupp ? 16 ? k ramp compensation level on pin 1 ? rramp = 100 k 2 rlevel ? 2.75 ? v skip cycle generation internal skip mode level, in percentage of maximum peak current ? iskip ? 25 ? % protections brown?out level 3 vbo 510 570 620 mv brown?out hysteresis current, t j = 25 c (note 3) 3 ibohyste 10 11.5 13 a brown?out hysteresis current, t j = 0 c to 125 c 3 ibohyste ? 10 ? a fault validation further to error flag assertion ? timeron 40 55 ? ms off phase in fault mode ? timeroff ? 440 ? ms latching voltage on brown?out pin 3 vlatch 3.15 3.5 3.85 v latch input integrating filter time constant 3 tdelbol ? 20 ? s ovp integrating filter time constant ? tdelovp ? 50 ? s v cc current at which the switcher stops pulsing 1 iovp 6.0 8.5 11 ma tempera ture management temperature shutdown ? tsd 160 ? ? c hysteresis in shutdown ? ? ? 40 ? c 3. see characterization curves for full temperature span evolution. 4. the final switch current is: ipeak_2x_cs + tprop x vin / lp, with vin the input voltage and lp the primary inductor in a flyb ack. 5. oscillator frequency is measured with disabled jittering.
ncp1027 http://onsemi.com 6 11 10 9 8 7 6 140 120 100 80 60 40 20 0 ?20 temperature ( c) iovp (ma) 7.9 8.0 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 ?20 0 20 40 60 80 100 120 14 0 temperature ( c) v ccon (v) temperature ( c) 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 ?20 0 20 40 60 80 100 120 140 temperature ( c) v ccmin (v) 14 0 120 100 80 60 40 20 0 ?20 temperature ( c) v ccclamp (v) 0.14 0.16 0.18 0.20 0.22 0.24 1.0 1.2 1.4 1.6 1.8 ?20 0 20 40 60 80 100 120 140 icc1 (ma) 350 400 450 500 550 600 650 700 750 800 850 900 ?20 0 20 40 60 80 100 120 14 0 temperature ( c) ic2 ( a) figure 3. figure 4. figure 5. figure 6. figure 7. figure 8.
ncp1027 http://onsemi.com 7 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 ?20 0 20 40 60 80 100 120 140 temperature ( c) ic1 (ma) 59.0 60.0 61.0 62.0 63.0 64.0 65.0 66.0 67.0 68.0 69.0 70.0 71.0 ?20 0 20 40 60 80 100 120 140 temperature ( c) fosc (khz) 75.0 77.0 79.0 81.0 83.0 85.0 87.0 ?20 0 20 40 60 80 100 120 140 temperature ( c) dmax (%) figure 9. figure 10. figure 11. figure 12. 0 20 40 60 80 100 120 temperature ( c) fosc (khz) temperature ( c) ?20 0 20 40 60 80 100 120 140 temperature ( c) 510 520 530 540 550 560 570 580 590 600 610 vbo (mv) 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 ?20 0 20 40 60 80 100 120 140 ibo hysteresis ( a) figure 13. figure 14. ?40 ?20 0 20 40 60 80 100 120 140
ncp1027 http://onsemi.com 8 ?20 0 20 40 60 80 100 120 140 temperature ( c) vlatch (v) 3.2 3.3 3.4 3.5 3.6 3.7 3.8 figure 15. ?20 0 20 40 60 80 100 120 1 40 temperature ( c) r ds(on) @ id = 100 ma ( ) 2 3 4 5 6 7 8 9 10 11 figure 16. 720 740 760 780 800 820 840 860 880 temperature ( c) ?20 0 20 40 60 80 100 120 140 ipeak (ma) figure 17. 16 18 20 22 24 26 28 30 ?20 0 20 40 60 80 100 120 1 40 temperature ( c) iopp (%) ipin 7 = 40 a ?20 0 20 40 60 80 100 120 140 temperature ( c) tleb + tpropdelay (ns) 200 220 240 260 280 300 320 340 360 380 400 figure 18. figure 19. 2.5 2.6 2.7 2.8 temperature ( c) ?20 0 20 40 60 80 100 120 14 0 ramp compensation level (v) figure 20.
ncp1027 http://onsemi.com 9 ?20 0 20 40 60 80 100 120 140 temperature ( c) timeron (ms) 50 52 54 56 58 60 62 64 66 68 70 figure 21. ?20 0 20 40 60 80 100 120 140 temperature ( c) idss off ( a) 10 20 30 40 50 60 70 80 90 100 figure 22. 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 250 200 150 100 50 0 140 c 125 c 85 c 25 c 0 c ?20 c ?40 c iopp ( a) ipeak reduction (%) figure 23. ipeak reduction = f(lopp, @ temperature)
ncp1027 http://onsemi.com 10 application information introduction the ncp1027 offers a complete current?mode control solution and enhances the ncp101x series. the component integrates everything needed to build a rugged and low?cost switch?mode power supply (smps) featuring low standby power. ? current?mode operation: the controller uses a current?mode control architecture, which, together with an adjustable ramp compensation circuitry, ensures efficient and stable continuous or discontinuous conduction designs. ? 700 v?5.8 power switch circuit: due to on semiconductor very high voltage integrated circuit technology, the circuit hosts a high?voltage power switch circuit featuring a 5.8 r ds(on) ? t j = 25 c. this value lets the designer build a 15 w power supply operated on universal mains as long as sufficient copper area exists to lower the junction?to?ambient thermal resistance. an internal current source delivers the startup current, necessary to crank the power supply. ? short?circuit protection: by permanently monitoring the feedback line activity, the circuit is able to detect the presence of a short?circuit, immediately reducing the output power for a total system protection. a 55 ms timer is started as soon as the feedback pin asks for the maximum peak current. at the end of this timer, if the fault is still present, then the device enters a safe, auto?recovery burst mode, affected by a fixed 440 ms recurrence. once the short has disappeared, the controller resumes and goes back to normal operation. the timer duration is fully independent from the v cc capacitor value. ? over power protection: a possibility exists to reduce the maximum output power capability in high line conditions. a simple two resistor network wired to the bulk capacitor will program the maximum current reduction for a given input voltage (down to 20% of the maximum peak current). ? fail?safe optocoupler/overvoltage protection: as the auxiliary winding is connected to the v cc pin, an internal active clamp connected between v cc and ground limits the supply dynamics to 8.7 v. in case the current injected in this clamp exceeds a level of 6.0 ma (minimum), the controller immediately stops switching and waits a full timer period before attempting to restart. if the default is gone, the controller resumes operation. if the default is still there, e.g. a broken optocoupler, the controller protects the load through a safe burst mode. ? brown?out input: a fraction of the input voltage appears on pin 3, due to a resistive divider. if the mains drops below a level adjusted by this resistive divider, the circuit does not switch. as soon as the mains goes back within its normal range, the device resumes operation and operates normally. by adjusting the bridge resistors, it becomes possible to set the brown?out levels (on and off) independently. ? latchoff: pin 3 also welcomes a comparator who offers a way to fully latch the controller. if an external event (e.g. an overtemperature) brings the brown?out pin above 3.5 v, the circuit stays permanently off until the user cycles its v cc down, for instance by unplugging the converter from the mains outlet. ? frequency jittering: the internal clock receives a low frequency modulation which helps smoothing the power supply emi signature. ? soft?start: a 1.0 ms soft?start ensures a smooth startup sequence, reducing output overshoots. ? skip cycle: if smps naturally exhibit a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping unneeded switching cycles, the ncp1027 drastically reduces the power wasted during light load conditions. experiments carried over the 5.0 v/2.0 a demonstration board reveal a standby power at no?load and 265 vac of 85 mw and an efficiency for 500 mw output power of 64% at 230 vac.
ncp1027 http://onsemi.com 11 startup sequence the ncp1027 includes a high?voltage startup circuitry, directly deriving current from the bulk line to charge the v cc capacitor. figure 24 details the simplified internal arrangement. vbulk i1 rv cc 1 i2 + cv cc i clamp vz = 8.7 v i clamp > 6 ma ovp fault icc1 + ? v ccon v ccoff + 5 8 + ic1 figure 24. internal arrangement of the startup circuitry when the power supply is first connected to the mains outlet, the internal current source is biased and charges up the v cc capacitor. when the voltage on this v cc capacitor reaches the vcc on level (typically 8.5 v), the current source turns off, reducing the amount of power being dissipated. at this time, the v cc capacitor only supplies the controller, and the auxiliary supply should take over before v cc collapses below vcc (min) . this v cc capacitor, cv cc , must therefore be calculated to hold enough energy so that v cc stays above vcc (min) (7.3 v typical) until the auxiliary voltage fully takes over. an auxiliary winding is needed to maintain the v cc in order to self?supply the switcher. the v cc capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. as one can see in figure 24 , an internal active zener diode, protects the switcher against lethal v cc runaways. this situation can occur if the feedback loop optocoupler fails, for instance, and you would like to protect the converter against an over voltage event. in that case, the internal current increase incurred by the v cc rapid growth triggers the over voltage protection (ovp) circuit and immediately stops the output pulses for 440 ms. then a new startup attempt takes place to check whether the fault has disappeared or not. the ovp paragraph gives more design details on this particular section. the v cc capacitor can be calculated knowing a) the amount of energy that needs to be stored; b) the time it takes for the auxiliary voltage to appear, and; c) the current consumed by the controller at that time. for a better understanding, figure 25 shows how the voltage evolves on the v cc capacitor upon startup.
ncp1027 http://onsemi.com 12 figure 25. a typical startup sequence showing the v cc capacitor voltage evolution versus time. suppose our power supply takes 10 ms (t startup ) to bring the output voltage to its target value. we know that the switcher consumption is around 2.0 ma (i cc1 ). therefore, we can calculate the amount of capacitance we need, to hold v cc above 7.5 v at least for 10 ms while delivering 2.0 ma: c i cc1 t startup v cc or, by replacing with the above values, c 2m 10 m 1 20 f then select a 33 f for the v cc capacitor. fault condition ? short?circuit on v cc in some fault situations, a short?circuit can purposely occur between v cc and gnd. in high line conditions (v hv = 370 v dc ) the current delivered by the startup device will seriously increase the junction temperature. for instance, since ic1 equals 3.0 ma (the min corresponds to the highest t j ), the device would dissipate 370 3 m = 1.1 w. to avoid this situation, the controller includes a novel circuitry made of two startup levels, ic1 and ic2. at powerup, as long as v cc is below a 1.3 v level, the source delivers ic1 (around 650 a typical), then, when v cc reaches 1.3 v, the source smoothly transitions to ic2 and delivers its nominal value. as a result, in case of short?circuit between v cc and gnd, the power dissipation will drop to 370 650 = 240 mw. figure 26 portrays this particular behavior. figure 26. the startup source now features a dual?level startup current. the first startup period is calculated by the formula c v = i t, which implies a 33 1.3/650 = 66 ms startup time for the first sequence (t 1 ). the second sequence (t 2 ) is obtained by toggling the source to 4.0 ma with a delta v of vcc on ? vccth = 8.5 ? 1.5 = 7.0 v, which finally leads to a second startup time of 7 33 /6.0 m = 39 ms. the total startup time becomes 66 m + 39 m = 105 ms as a typical value. please note that this calculation is approximated by the presence of the knee in the vicinity of the transition.
ncp1027 http://onsemi.com 13 fault condition ? output short?circuit as soon as v cc reaches vcc on , drive pulses are internally enabled. if everything is correct, the auxiliary winding increases the voltage on the v cc pin as the output voltage rises. during the start?sequence, the controller smoothly ramps up the peak current to imax setting, e.g. ipeak_hi, which is reached after a typical period of 1.0 ms. as soon as the peak current setpoint reaches its maximum (during the startup period but also anytime an overload occurs), an internal error flag is asserted, ipflag, indicating that the system has reached its maximum current limit set point (ip = ip max). the assertion of this flag triggers a 55 ms counter. if at counter completion ipflag remains asserted, all driving pulses are stopped and the part stays off during eight periods of 55 ms (440 ms). a new attempt to restart occurs and will last 55 ms providing the fault is still present. if the fault still affects the output, a safe burst mode is entered, affected by a low duty?cycle operation (11%). when the fault disappears, the power supply quickly resumes operation. figure 27 depicts this particular mode. figure 27. in case of short?circuit or overload, the ncp1027 protects itself and the power supply via a low frequency burst mode. the v cc is maintained by the current source and self?supplies the controller.
ncp1027 http://onsemi.com 14 in figure 27, one can see that the v cc is still alive, testifying for a badly coupled power secondary and primary auxiliary windings. some situations exist where an output short?circuit make the auxiliary winding collapse before the timer completion. in this particular case, the undervoltage lock out (uvlo) circuitry has the priority and safely cuts off all driving pulses. figure 28 describes this variation. figure 28. the auxiliary winding collapses in presence of a short?circuit. pulses are immediately stopped as v cc crosses the minimum operating voltage, vcc (min) .
ncp1027 http://onsemi.com 15 fault condition ? output too low this particular mode of operation occurs when the feedback is ensured by a two?loop control imposing either constant output voltage (cv) or constant output current (cc), for instance in a battery charger. in cc mode, the output voltage falls down below the original target but the feedback loop is kept closed by the cc controller. for that reason, the controller becomes un?able to detect a real output short?circuit since ipflag will never be asserted. due to a good winding coupling, the primary side auxiliary collapsing will ensure a proper fault detection via the uvlo internal circuit. figure 29 depicts this operating way. figure 29. in this particular case, the output goes low but the timer is not started since the fb pin is still held by the optocoupler. due to the uvlo circuit, the controller safely stops operation at v cc = vcc (min) .
ncp1027 http://onsemi.com 16 fault condition ? low input voltage the ncp1027 includes a brown?out circuitry able to protect the power supply in case of low input voltage conditions. figure 30 shows how internally the ncp1027 monitors the voltage image of the bulk capacitor. below a given level, the controller blocks the driving pulses, above it, it authorizes them. the internal circuitry, depicted by figure 30a, offers a way to observe the high?voltage (hv) rail. a resistive divider made of r upper and r lower , brings a portion of the hv rail on pin 3. below the turn?on level, the 10 a current source ibo is off. therefore, the turn?on level solely depends on the division ratio brought by the resistive divider. + ? bo on/off v dd ibo bo vbulk rupper rlower + vbo 1 vin 2 vcmp 20.0u 60.0u 100u 140u 180u time in seconds 0 40.0 80.0 120 160 0 4.00 8.00 12.0 16.0 plot1 2 1 vcmp volts vin in volts vbulk = 100 v vbulk = 70 v figure 30a. the internal brown?out configuration with an offset current source. figure 30b. simulation results for 100/70 on/off levels. figure 30. to the contrary, when the internal bo signal is high, the ibo source is activated and creates an hysteresis. as a result, it becomes possible to select the turn?on and turn?off levels via a few lines of algebra. ibo is off (eq. 1 ) v( ) v bulk1 r lower r lower r upper ibo is on (eq. 2) v( ) v bulk2 r lower r lower r upper ibo r lower r upper r lower r upper we can now extract r lower from equation 1 and plug it into equation 2, then solve for r upper : r upper r lower v bulk1 ?vbo vbo r lower vbo v bulk1 ?v bulk2 ibo (v bulk1 ?vbo) if we decide to turn?on our converter for vbulk1 equals 100 v and turn it off for vbulk2 equals 70 v, then we obtain: r upper = 3.0 m r lower = 18 k
ncp1027 http://onsemi.com 17 the bridge power dissipation is 330 2 /3.018 meg = 36 mw in nominal high?line operation. figure 30b simulation result confirms our calculations. figure 31 describes signal variations during a brown?out condition. please note that output pulses only reappear when v cc reaches v cc(on) , ensuring a clean startup sequence. as in fault mode conditions, the startup source is activated on and off and self?supplies the controller in a dynamic self?supply (dss) mode. figure 31. signal evolution during a brown?out condition depending on input surge tests, it might be necessary to wire a filtering capacitor between bo and gnd (close to the circuit) to avoid adversely triggering the internal latch (unless this is a wanted feature) when the pulse train appears. latchoff protection there are some situations where the converter shall be fully turned?off and stay latched. this can happen in the presence of a secondary overvoltage (the feedback loop is drifting) or when an overtemperature is detected. secondary monitoring is usually implemented when the coupling between auxiliary and power windings does not lead to a precise primary detection, hence the auto?recovery ovp on pin 1 would not satisfy the precision requirements. due to the addition of a comparator on the bo pin, a simple external circuit can lift up this pin above vlatch and permanently disable pulses. the v cc needs to be cycled down below 3.5 v typically to reset the controller.
ncp1027 http://onsemi.com 18 + ? vout + vlatch ntc v cc q1 vbulk rlower rupper bo 20 s rc to permanent latch ibo v dd + ? bo + vbo figure 32. adding a comparator on the bo pin offers a way to latch?off the controller. in figure 32, q1 is blocked and does not bother the bo measurement as long as the ntc and the optocoupler are not activated. as soon as the secondary optocoupler senses an ovp condition, or the ntc reacts to a high ambient temperature, q1 base is brought to ground and the bo pin goes up, permanently latching off the controller. figure 33 depicts the converter behavior in case of total latch?off. figure 33. if the bo pin is lifted up to vlatch, the controller permanently latches off.
ncp1027 http://onsemi.com 19 auto?recovery overvoltage protection the particular ncp1027 arrangement offers a simple way to prevent output voltage runaway when the optocoupler fails. as figure 34 shows, an active zener diode monitors and protects the v cc pin. below its equivalent breakdown voltage, that is to say 8.7 v typical, no current flows in it. if the auxiliary v cc pushes too much current inside the zener, then the controller considers an ovp situation and stops the pulses. figure 34 shows that the insertion of a resistor ( r limit ) between the auxiliary dc level and the v cc pin is mandatory a) not to damage the internal 8.7 v zener diode during an overshoot for instance (absolute maximum current is 15 ma) b) to implement the fail?safe optocoupler protection (ovp) as offered by the active clamp. please note that there cannot be bad interaction between the clamping voltage of the internal zener and vcc on since this clamping voltage is actually built on top of vcc on with a fixed amount of offset (200 mv typical). r limit should be carefully selected to avoid triggering the ovp as we discussed, but also to avoid disturbing the v cc in low/light load conditions. the following details how to evaluate the r limit value. self?supplying controllers in extremely low standby applications often puzzles the designer. actually, if an smps operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 v (v nom ), this voltage can drop below 10 v (v stby ) when entering standby. this is because the recurrence of the switching pulses expands so much, that the low frequency refueling rate of the v cc capacitor is not enough to keep a proper auxiliary voltage. figure 35 portrays a typical scope shot of an smps entering deep standby (output unloaded). thus, care must be taken when calculating r limit 1) to not trigger the v cc overcurrent latch (by injecting 6.0 ma into the active clamp ? always use the minimum value for worse case design) in normal operation but 2) not to drop too much voltage over r limit when entering standby. otherwise, the converter will enter burst mode as it will sense an uvlo condition. based on these recommendations, we are able to bound r limit between two equations: (eq. 3) v nom ?v clamp i trip r limit v stby ?v ccon icc1 where: v nom is the auxiliary voltage at nominal load. v stdby is the auxiliary voltage when standby is entered. i trip is the current corresponding to the nominal operation. it thus must be selected to avoid false tripping in overshoot conditions. always use the minimum of the specification for a robust design. icc1 is the controller consumption. this number slightly decreases compared to icc1 from the spec since the part in standby does almost not switch. it is around 1.0 ma for the 65 khz version. vcc (min) is the level above which the auxiliary voltage must be maintained to keep the controller away from the uvlo trip point. it is good to obtain around 8.0 v in order to offer an adequate design margin, e.g. to not reactivate the startup source (which is not a problem in itself if low standby power does not matter). + ? + ? + v ccon = 8.5 v v cc(min) = 7.5 v startup source drain + + ? v clamp = 8.7 v typ. latch + i > 6 ma ground v cc + c vcc + c aux l aux r limit d1 figure 34. a more detailed view of the ncp1027 offers better insight on how to properly wire an auxiliary winding. since r limit shall not bother the controller in standby, e.g. keep vauxiliary to around 8.0 v (as selected above), we purposely select a vnom well above this value. as explained before, experience shows that a 40% decrease can be seen on auxiliary windings from nominal operation down to standby mode. let?s select a nominal auxiliary winding of 20 v to offer sufficient margin regarding 8.0 v when in standby ( r limit also drops voltage in standby ).
ncp1027 http://onsemi.com 20 plugging the values in equation 3 gives the limits within which r limit shall be selected: 20?8.7 6m rlimit 12?8 1m , that is say : 1.8 k
r limit
4k . to if we design a 65 khz power supply delivering 12 v, then the ratio between auxiliary and power must be: 12/20 = 0.6. the ovp latch will activate when the clamp current exceeds 6.0 ma. this will occur when v auxiliary grows up to: 1. 8.7 + 1.8 k (6 m + 1.8 m) 23 v for the first boundary ( r limit = 1.8 k ). 2. 8.7 + 4 k (6 m + 1.8 m) 40 v for the second boundary ( r limit = 4.0 k ). due to a 0.6 ratio between the auxiliary v cc and the power winding, the auxiliary ovp will be seen as a lower overshoot on the real output: 1. 23 0.6 13.8 v 2. 40 0.6 24 v as one can see, tweaking the r limit value will allow the selection of a given overvoltage output level. theoretically predicting the auxiliary drop from nominal to standby is an almost impossible exercise since many parameters are involved, including the converter time constants. fine tuning of r limit thus requires a few iterations and experiments on a breadboard to check the auxiliary voltage variations but also the output voltage excursion in fault. once properly adjusted, the fail?safe protection will preclude any lethal voltage runaways in case a problem would occur in the feedback loop. figure 35. the burst frequency becomes so low that it is difficult to keep an adequate level on the auxiliary v cc . > 30 ms figure 36 describes the main signal variations when the part operates in auto?recovery ovp. figure 36. if the v cc current exceeds a certain threshold, an auto?recovery protection is activated and protects the design.
ncp1027 http://onsemi.com 21 improving the precision in auto?recovery ovp given the ovp variations the internal trip current dispersion incur, it is sometimes more interesting to explore a different solution, improving the situation to the cost of a minimal amount of surrounding elements. figure 37 shows that adding a simple zener diode on top of the limiting resistor, offers a better precision since what matters now is the internal 8.7 v v cc breakdown, plus the zener voltage. a resistor in series with the zener diodes keeps the maximum current in the v cc pin below the maximum rating of 15 ma just before tripping the ovp. ground v cc + l aux r limit d1 figure 37. a simple zener diode added in parallel with r limit , allows for a better precision ovp. figure 38. internal logic blocks take a certain amount of time before shutting off the driving pulses in presence of an overcurrent event. over power compensation over power compensation or protection (opp) represents a way to limit the effects of the propagation delay when the converter is supplied from its highest input voltage. the propagation delay naturally extends the power capability of any current?limited converter. figure 38 explains why. the main parameter is the on slope, that is to say, the pace at which the inductor current grows?up when the power switch closes. for a flyback controller, the slope is given by: s on v in l p (eq. 4) where l p is the transformer magnetizing/primary inductance and v in , the input voltage. as the internal logic takes some time to react, the switch gate shutdown does not immediately occur when the maximum power limit is detected (just before activating the overload protection circuit). clearly speaking, it can take up to 100 ns for the ncp1027 current sense comparator to propagate through the various logical gates before reaching the power switch and finally shutting it off. this is the well?known propagation delay noted t prop . unfortunately, during this time, the current keeps growing as figure 38 depicts. the peak current will therefore be troubled by this propagation delay. the formula to obtain the final value is simply: i peak, final v in l p t (eq. 5) i peak, max prop at low line, s on is relatively low and does not bother the final peak value. the situation differs at high line and induces a higher peak current. therefore, the power supply output power capability increases with the input voltage. let us a take a look at a simple example. suppose the peak current is 700 ma: l p = 1.0 mh v in lowline = 100 vdc v in highline = 350 vdc i peak,max = 700 ma t prop = 100 ns p out 1 2 i 2 peak, final f sw l p (eq. 6) where: f sw is the switching frequency and the ef ficiency. usually is bigger in high line conditions than in low line conditions. this formula is valid for a discontinuous conduction mode flyback. from equation 5, we can calculate the final peak current in both conditions: i peak,final = (100/1m) x 100n + 700m = 710 ma at low line. i peak,final = (350/1m) x 100n + 700m = 735 ma at high line. from equation 6, we can have an idea of the maximum output power capability again, in both conditions with respective low and high line efficiency numbers of 78% and 82% for instance: p out,lowline = 0.5 0.71 2 1m 65k 0.78 = 12.8 w p out,highline = 0.5 0.735 2 1m 65k 0.82 = 14.4 w
ncp1027 http://onsemi.com 22 this difference might not be seen as a problem, but some design specifications impose stringent conditions on the maximum output current capability, regardless the line input. hence the need for an opp input since we want to limit the power to 12.8 w at high line, let us calculate the needed peak current: from equation 6: i peak 2p out f sw l p = 693 ma to deliver 12.8 w at high line. compared to our 735 ma, we need to decrease the setpoint by 6% roughly when v in equals 350 vdc. the ncp1027 hosts a special circuitry looking at the couple voltage/current present on pin 7. figure 39 shows how to arrange components around the controller to obtain over power protection. current setpoint over power protection opp bulk roppu roppl gnd figure 39. a resistive network reduces the power capability in high?line conditions. first, you need to know the required injected current and the voltage across pin 7 to start activating opp. experiments consist in wiring figure 39 circuit and running the power supply in conditions where it must shut down (e.g. highest input voltage and maximum output current per specification). for this, r oppl can be put to 10 k and r oppu made of a series string of 4 1.0 m resistors plus a 10?turn 1.0 m potentiometer set at its maximum value. an amp?meter is inserted in series with pin 7 and a volt?meter monitors its voltage with respect to ground. once the power supply is powered, slowly rotate the potentiometer and observe both voltage and current going up at pin 7. at a certain time, as voltage and current increase, the controller will shut down the power supply. the current at this time is the one we are looking for. suppose these experiments lead to 80 a with a pin 7 activation voltage of 2.45 v. final resistor equations are: vbulkh = 375 vdc ; the maximum voltage at which opp must shut down the controller v bulkl = 200 vdc ; the minimum voltage below which opp is not activated i opp = 80 a ; the current in pin 7 v f = 2.45 v ; the voltage of pin 7 at the above condition r oppl v bulkh ?v bulkl i opp (v bulkl ?v f ) v f 27 k (eq. 7) r opph r oppl v bulkl ?v f v f 2.2 m (eq. 8) if the opp feature is not needed for some designs, it is possible to ground it via a copper wire to the adjacent ground pin. this can help to develop a larger copper area in an application where the thermal resistance is an important parameter. ramp compensation when operating in continuous conduction mode (ccm), current?mode power supplies can exhibit so?called sub?harmonic oscillations. to cure this problem, the designer must inject ramp compensation. the ramp can either be added to the current sense information or directly subtracted from the feedback signal. figure 40 details the internal arrangement of the ramp compensation circuitry. gate reset ramp rr vp v dd irr control figure 40. the internal feedback chain and the ramp compensation network
ncp1027 http://onsemi.com 23 the principle consists in selecting the rr resistor, connected from pin 2 to ground, to impose a current i rr in the transistor collector. figure 41. maximum peak current setpoint variations versus ramp compensation the equation to get the right compensation level is the following: rr v p 2.75 k s a @t sw (eq. 9) where vp, the total voltage swing, equals 2.75 v. application example: suppose we have the following flyback specifications: vout = 5.0 v output voltage vf = 1.0 v secondary diode forward drop @ iout nominal np:ns = 1:n = 1:0.052 transformer turn ratio lp = 3.8 mh primary inductance we can calculate the off slope, the one actually needed to evaluate s a , by reflecting the output voltage over the primary inductance. the slope is projected over a complete switching period. here, we use a 65 khz part. s off v out v f nl p t sw 6 15u 0.052 3.8m 455 ma 15 s (eq. 10 ) due to the internal sense arrangement, this current slope will become a voltage slope having a value of: s off 455m 0.375 170 mv 15 s (eq. 11) if we chose 50% of this downslope, then the final compensation ramp will present a slope of: s a 170m 2 85 mv 15 s (eq. 12) we then have: rr v p 2.75 k s a @t sw 2.75 2.75k 85m 89 k (eq. 13) in the above calculations, the internal esd resistor has purposely been omitted to avoid bringing in another variable. in case no ramp compensation is required, pin 2 must be tied to v cc , the adjacent pin. soft?start the ncp1027 features a 1.0 ms soft?start, which reduces the power?on stress, but also contributes to lower the output overshoot. figure 42 shows a typical operating waveform. the ncp1027 features a novel patented structure which offers a better soft?start ramp, almost ignoring the startup pedestal inherent to traditional current?mode supplies. figure 42. 1.0 ms soft?start sequence
ncp1027 http://onsemi.com 24 jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. the ncp1027 offers a 6% deviation of the nominal switching frequency. the sweep sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 hz. figure 43 shows the relationship between the jitter ramp and the frequency deviation. it is not possible to externally disable the jitter. 65khz 68.9khz 61.1khz jitter ramp internal sawtooth adjustable figure 43. modulation effects on the clock signal by the jittering sawtooth skip?cycle skip cycle offers an efficient way to reduce the standby power by skipping unwanted cycles at light loads. however, the recurrent frequency in skip often enters the audible range and a high peak current obviously generates acoustic noise in the transformer. the noise takes its origins in the resonance of the transformer mechanical structure which is excited by the skipping pulses. a possible solution, successfully implemented in the ncp1200 series, also authorizes skip cycle but only when the power demand as dropped below a given level. this is what figure 44 shows, as implemented on the ncp1027. 0 skip cycle current limit nominal peak current figure 44. low peak current skip cycle guarantees noise?free operation
ncp1027 http://onsemi.com 25 5.0 v/3.0 a universal mains power supply due to its low r ds(on) , the ncp1027 can be used in universal mains smps up to 15 w of continuous power, provided that the chip power dissipation is well under control. that is to say that average power calculations and measurements have been carried and correlated. the design of an smps around a monolithic device does not differ from that of a standard circuit using a controller and a mosfet. however, one needs to be aware of certain characteristics specific of monolithic devices. let us follow the steps: v in min = 120 vdc v in max = 375 vdc v out = 5.0 v v out = 15 w operating mode is ccm = 0.8 1. the lateral mosfet body?diode shall never be forward biased, either during startup (because of a large leakage inductance) or in normal operation as shown by figure 45. this condition sets the maximum voltage that can be reflected during t off . 1.004m 1.011m 1.018m 1.025m 1.032m ? 50.0 50.0 150 250 350 > 0 !! figure 45. the reflected voltage shall always be greater than the minimum input voltage to avoid the forward biasing of the mosfet body?diode. figure 46. primary inductance current evolution in ccm as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you thus must adopt a turn ratio which adheres to the following equation: n(v out v f )
v in, min
vin min (eq. 14) . in our case, since we operate from a 120 v dc rail while delivering 5.0 v, we can select a reflected voltage of 110 v dc maximum: 120?110 > 0. therefore, the turn ratio np:ns must be smaller than v in v out v f 110 5 1 18.3 or np : ns
19 . we will see later on how it affects the calculation. 2. lateral mosfets have a poorly doped body?diode which naturally limits their ability to sustain the avalanche. a traditional rcd clamping network shall thus be installed to protect the mosfet. in some low power applications, a simple capacitor can also be used since vdrain max v in n(v out v f ) i peak l f c tot (eq. 15) , where l f is the leakage inductance, c tot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), n the np:ns turn ratio, v out the output voltage, v f the secondary diode forward drop and finally, i peak the maximum peak current. worse case occurs when the smps is very close to regulation, e.g. the v out target is almost reached and i peak is still pushed to the maximum. for this design, we have selected our maximum voltage around 650 v (at v in = 375 vdc). this voltage is given by the rcd clamp installed from the drain to the bulk voltage. we will see how to calculate it later on. 3. calculate the maximum operating duty?cycle for this flyback converter operated in ccm: d max nv out nv out v in, min 1 1 v in,min nv out 0.49 (eq. 16 ) 4. to obtain the primary inductance, we have the choice between two equations: l (v in d) 2 f sw kp in (eq. 17) , where k i l i 1 and defines the amount of ripple we want in ccm (see figure 46). ? small k: deep ccm, implying a large primary inductance, a low bandwidth and a large leakage inductance.
ncp1027 http://onsemi.com 26 ? large k: approaching bcm where the rms losses are the worse, but smaller inductance, leading to a better leakage inductance. from equation 16, a k factor of 0.8 (40% ripple), gives an inductance of: l (120 0.49) 2 60k 0.8 18.75 3.8 mh i l v in d lf sw 120 0.49 3.8m 60k 258 ma peak to peak the peak current can be evaluated to be: i peak i avg d i l 2 i peak 156m 0.49 i l 2 447 ma in figure 46, i 1 can also be calculated: i 1 i peak ? i l 2 0.447?0.129 318 ma 5. based on the above numbers, we can now evaluate the conduction losses: i d, rms i 1 d 1 1 3 i l 2i 1 2 0.318 0.7 1 1 3 0.258 2 0.318 2 228 ma rms if we take the maximum r ds(on) for a 120 c junction temperature, i.e. 11 , then conduction losses worse case are: p cond i 2 d, rms r ds(on) 571 mw 6. off?time and on?time switching losses can be estimated based on the following calculations: p off i peak v ds t off 6t sw 0.447 650 40n 6 15u 130 mw (eq. 18) p on i peak n(v out v f )t on 6t sw (eq. 19) 0.447 114 40n 6 15u 22 mw the theoretical total power is then 0.571 + 0.13 + 0.022 = 723 mw. 7. the ramp compensation will be calculated as suggested by equation 13 giving a resistor of 78 k or 82 k for the normalized value. power switch circuit protection as in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the power switch circuit bvdss which is 700 v. figures 47a, b, c present possible implementations: + 1 2 3 4 5 7 8 figure 47. different options to clamp the leakage spike 6 cv cc c hv + 1 2 3 4 5 7 8 6 cv cc hv r clamp c clamp d + 1 2 3 4 5 7 8 6 cv cc hv d dz a. b. c. figure 47a: the simple capacitor limits the voltage according to equation 14. this option is only valid for low power applications, e.g. below 5.0 w, otherwise chances exist to destroy the mosfet. after evaluating the leakage inductance, you can compute c with equation 15. typical values are between 100 pf and up to 470 pf. large capacitors increase capacitive losses figure 47b: the most standard circuitry called the rcd network. you calculate r clamp and c clamp using the following formulae: r clamp 2v clamp (v clamp ?(v out v f )n) l peak i 2 peak f sw (eq. 20) c clamp v clamp v ripple f sw r clamp (eq. 21)
ncp1027 http://onsemi.com 27 clamp is usually selected 50?80 v above the reflected value n (v out + v f ). the diode needs to be a fast one and an mur160 represents a good choice. one major drawback of the rcd network lies in its dependency upon the peak current. worse case occurs when i peak and v in are maximum and v out is close to reach the steady?state value. figure 47c: this option is probably the most expensive of all three but it offers the best protection degree. if you need a very precise clamping level, you must implement a zener diode or a tvs. there are little technology differences behind a standard zener diode and a tvs. however, the die area is far bigger for a transient suppressor than that of zener. a 5.0 w zener diode, like the 1n5388b, will accept 180 w peak power if it lasts less than 8.3 ms. if the peak current in the worse case (e.g. when the pwm circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 w, then the diode will be destroyed when the supply experiences overloads. a transient suppressor like the p6ke200 still dissipates 5.0 w of continuous power, but is able to accept surges up to 600 w @ 1.0 ms. select the zener or tvs clamping level between 40 to 80 v above the reflected output voltage when the supply is heavily loaded. power dissipation and heatsinking the ncp1027 hosting a power switch circuit and a controller, it is mandatory to properly manage the heat generated by losses. if no precaution is taken, risks exist to trigger the internal thermal shutdown (tsd). to help dissipating the heat, the pcb designer must foresee large copper areas around the pdi7 package. when surrounded by a surface greater than 1.0 cm of 35 m copper, it becomes possible to drop the thermal resistance junction?to?ambient, r ja down to 75 c/w and thus dissipate more power. the maximum power the device can thus evacuate is: p max t j max ?t amb max r ja (eq. 22) which gives around 930 mw for an ambient of 50 c and a maximum junction of 120 c. the losses inherent to the switch circuit r ds(on) can be theoretically evaluated, but the final prototype evaluation must include board measurements to confirm that the junction temperature stays within safe limits. figure 48 gives a possible layout to help dropping the thermal resistance. when measured on a 70 m (2 oz.) copper thickness pcb, we obtained a thermal resistance of 75 c/w. figure 48. a possible pcb arrangement to reduce the thermal resistance junction?to?ambient. when routing the printed circuit, it is important to keep high impedance line very short, like the brown?out signal and the opp input if used. application diagram figure 49 displays the final application schematic. the output uses a tl v431 whose low bias current represents an advantage for low standby power switch mode supplies. the secondary side features an additional lc filter needed to remove unwanted spikes, although less problematic than in dcm operation. on the primary side, a resistive network senses the input bulk voltage and prevents the controller from turning on for input voltages below 100 vdc. the auxiliary winding delivers 20 v nominal and thus offers comfortable margin when the converter enters standby. as we do not use any opp, pin 7 goes to ground and offers extended possibility to layout more copper area.
ncp1027 http://onsemi.com 28 85?265 vac + + 1 2 3 45 7 8 u2 ncp1027 c13 220 nf type = x2 c4 47 f/ 400 v r1 2.8 m r10 200 k r3 18 k c1 10 n cv cc 47 f r2 78 k c12 100 p r9 5.6 k 20 v + c11 1 f d2 1n4637 r5 150 k type = 1w c7 10 nf type = 400 v + c5 470 f + c8 470 f + c9 470 f d1 mbrd640ctt4 c10 2.2 nf type = y1 r4 100 u1 tl431 r11 1 k r6 10 k + c3 100 f c2 100 nf r7 10 k vout 5 v @ 3 a l2 2.2 h np:ns = 1:0.062 np:naux = 1:0.208 lp = 3.8 mh figure 49. 5.0 v?3.0 a universal mains power supply d5 1n4637
ncp1027 http://onsemi.com 29 transformer specifications: vout = 5.0 v/3.0 a vaux = 20 v/10 ma lp = 3.8 mh ip, rms = 280 ma ip, max = 800 ma isec, rms = 5.0 a fsw = 65 khz np:nsec = 1 : 0.052 np:naux = 1 : 0.208
ncp1027 http://onsemi.com 30 package dimensions 8?lead pdip p suffix case 626a?01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. package contour optional (round or square corners). 4. dimension l to center of lead when formed parallel. 5. dimensions a and b are datums. 14 5 8 f note 3 ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m ??? 10 ??? 10 n 0.76 1.01 0.030 0.040 b a on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 ncp1027d the product described herein (ncp1027), may be covered by one or more of the following u.s. patents: 5,418,410; 5,477,175; 6,27 1,735; 6,362,067; 6,385,060; 6,429,709; 6,448,625; 6,492,679; 6,597,221; 6,633,193; 6,919,598; 6,940,320. there may be other patents p ending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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